MSc. Ghada Dessouky

Research Assistant

Mornewegstraße 30
D-64293 Darmstadt

Building: S4|14
Phone:+49 (0)6151 / 16 - 25320



Since November 2014

Research Assistant

at CYSEC and Technische Universität DarmstadtGermany


Research Assistant

at Institute of Parallel and Distributed Systems, Universität Stuttgart, Germany


MSc. Information Technology

(specialization in Embedded Systems Engineering) - INFOTECH Master’s Program

at Universität Stuttgart, Germany.

SS 2009

Bachelor thesis: DAAD Exchange Scholarship

“Design of Transconductor-based CAB for FPAA in 90nm CMOS Technology”
at Institute of Microelectronics, Universität Ulm, Germany

2005 - 2010

BSc. of Electronics Engineering

at Faculty of Information Engineering and Technology – German University in Cairo (GUC), Egypt

 Research Interests

  • Hardware-assisted security architectures
  • Embedded and digital systems design
  • Hardware/Software co-design
  • FPGA-based computing

Open HiWi Positions & Theses

We have open positions in the following projects:

  • Hardware-assisted security architectures and processor extensions
  • Using machine learning for anomaly detection
  • Verification of security properties of hardware designs

If you are familiar with digital design or machine learning and want to become part of one of our projects and participate in state-of-the-art research, please send us your application (CV, certificate(s) and any supporting documents) via email.




GarbledCPU: A MIPS Processor for Secure Computation in Hardware

Author Ebrahim Songhori, Shaza Zeitouni, Ghada Dessouky, Thomas Schneider, Ahmad-Reza Sadeghi, Farinaz Koushanfar
Date June 2016
Kind Inproceedings
Book title53rd Design Automation Conference (DAC'16)
Research Areas CASED, CROSSING, System Security Lab, ICRI-SC, S2, E4, Engineering Cryptographic Protocols, Secure Protocols, Primitives, P3, CYSEC
Abstract We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. Garbled-CPU provides three degrees of freedom for SFE which allow leveraging the trade-of between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.
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Previous Publications

Adaptive Dynamic On-Chip Memory Management for FPGA-based Reconfigurable Architectures
Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey, Sven Simon
In: 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014

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