MSc. Ghada Dessouky

Research Assistant

Mornewegstraße 30
D-64293 Darmstadt

Building: S4|14
Phone:+49 (0)6151 / 16 - 25320



Since November 2014

Research Assistant

at CYSEC and Technische Universität DarmstadtGermany


Research Assistant

at Institute of Parallel and Distributed Systems, Universität Stuttgart, Germany


MSc. Information Technology

(specialization in Embedded Systems Engineering) - INFOTECH Master’s Program

at Universität Stuttgart, Germany.

SS 2009

Bachelor thesis: DAAD Exchange Scholarship

“Design of Transconductor-based CAB for FPAA in 90nm CMOS Technology”
at Institute of Microelectronics, Universität Ulm, Germany

2005 - 2010

BSc. of Electronics Engineering

at Faculty of Information Engineering and Technology – German University in Cairo (GUC), Egypt

 Research Interests

  • Hardware-assisted security architectures
  • Embedded and digital systems design
  • Hardware/Software co-design
  • FPGA-based computing

Open HiWi Positions & Theses

We have open positions in the following projects:

  • Hardware-assisted security architectures and processor extensions
  • Using machine learning for anomaly detection
  • Verification of security properties of hardware designs

If you are familiar with digital design or machine learning and want to become part of one of our projects and participate in state-of-the-art research, please send us your application (CV, certificate(s) and any supporting documents) via email.




Automated Synthesis of Optimized Circuits for Secure Computation

Author Daniel Demmler, Ghada Dessouky, Farinaz Koushanfar, Ahmad-Reza Sadeghi, Thomas Schneider, Shaza Zeitouni
Date October 2015
Kind Inproceedings
Book title22nd ACM Conference on Computer and Communications Security (CCS'15)
LocationDenver, Colorado, USA
Research Areas System Security Lab, E4, CYSEC, Engineering Cryptographic Protocols, Solutions, S2, Primitives, P3, CROSSING, Engineering
Abstract In the recent years, secure computation has been the subject of intensive research, emerging from theory to practice. In order to make secure computation usable by non-experts, Fairplay (USENIX Security 2004) initiated a line of research in compilers that allow to automatically generate circuits from high-level descriptions of the functionality that is to be computed securely. Most recently, TinyGarble (IEEE S\&P 2015) demonstrated that it is natural to use existing hardware synthesis tools for this task. In this work, we present how to use industrial-grade hardware synthesis tools to generate circuits that are not only optimized for size, but also for depth. These are required for secure computation protocols with non-constant round complexity. We compare a large variety of circuits generated by our toolchain with hand-optimized circuits and show reduction of depth by up to 14\%. The main advantages of our approach are developing customized libraries of depth-optimized circuit constructions which we map to high-level functions and operators, and using existing libraries available in the industrial-grade logic synthesis tools which are heavily tested. In particular, we show how to easily obtain circuits for IEEE 754 compliant floating-point operations. We extend the open source ABY framework (NDSS 2015) to securely evaluate circuits generated with our toolchain and show between 0.5 to 21.4 times faster floating-point operations than previous protocols of Aliasgari et al. (NDSS 2013), even though our protocols work for two parties instead of three or more. As application we consider privacy-preserving proximity testing on Earth.
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Previous Publications

Adaptive Dynamic On-Chip Memory Management for FPGA-based Reconfigurable Architectures
Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey, Sven Simon
In: 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014

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