MSc. Shaza Zeitouni

Research Assistant

Mornewegstraße 30
D-64293 Darmstadt
GERMANY

Building: S4|14
Room:4.1.09
Phone:+49 (0)6151 / 16 - 25321
Email:shaza.zeitouni(a-t)trust.cased.de
Website:http://trust.cased.de/people/shaza-zeitouni/

 

Vita

Since 2014

Research Assistant

at Intel Collaborative Research Institute for Secure Computing (ICRI-SC),

Center for Advanced Security Research Darmstadt (CASED)

and Technische Universität Darmstadt, Germany

2012-2014

M.Sc. CSE

at Technische Universität Braunschweig, Germany

2001-2006

B.Sc. Electrical Engineering

at Aleppo University, Syria

 

 

Publications

GarbledCPU: A MIPS Processor for Secure Computation in Hardware

Author Ebrahim Songhori, Shaza Zeitouni, Ghada Dessouky, Thomas Schneider, Ahmad-Reza Sadeghi, Farinaz Koushanfar
Date June 2016
Kind Inproceedings
Book title53rd Design Automation Conference (DAC'16)
KeyTUD-CS-2016-0042
Research Areas CASED, CROSSING, System Security Lab, ICRI-SC, S2, E3, Engineering Cryptographic Protocols, Secure Protocols, Primitives, P3
Abstract We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. Garbled-CPU provides three degrees of freedom for SFE which allow leveraging the trade-of between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.
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